The present invention relates to a semiconductor memory device requiring refresh operations, and mainly to a technique that can be effectively utilized in a dynamic random access memory (DRAM), in which a read/write operation mainly from outside and a refresh operation by an internal circuit are executed within a single memory cycle.
In order to enable a DRAM to be handled in the same way as a static random access memory (SRAM) is handled, Japanese Unexamined Patent Publication No. Sho 61(1986)-71494 proposes a so-called time-multiplexed type DRAM in which a read/write operation and a refresh operation are carried out in a single cycle by allocating a separate time segment for each as shown in FIG. 37 or the two operations are carried out only when a read/write operation and a refresh operation are competing with each other.
According to the timing chart of FIG. 37, the completion of the refresh operation accomplished in the first half is detected by the precharge of a bit line to switch over to the read/write operation. While the chart shows a case in which the refresh operation is performed in the first half, it is also stated in the reference that the read/write operation can as well be performed in the first half to be followed by the refresh operation in the latter half.
In the time-multiplexed system described above, the completion of the refresh operation accomplished in the first half of the cycle is detected by the stand-by state of nodes within the memory and, in response to that, an external address is accepted in the latter half of the cycle to perform a usual write or read operation thereby to prevent any erroneous operation in memory selection or destruction of information stored in any memory cell. Therefore, in this time-multiplexed system, the two operations are completely separated in a time sequence to prevent erroneous operations or the like, inevitably inviting a problem of an extended cycle time.
In the above-described DRAM, if the period of time in which a word line is placed in a non-selected state, the precharging of the bit line is completed and the bit line takes on a high impedance state is kept from overlapping the next word line selecting operation, information in any memory cell can be protected from destruction. Viewed the other way around, if the word line is placed in a selecting state in the latter half of the cycle when the bit line is being precharged in the former half of the cycle, the precharge voltage of the bit line will be written into the selected memory cell as well and information stored therein will be destroyed. Taking note of this problem, the present inventor though of shortening the memory cycle of a DRAM operating in the time-multiplexed system described above.
An object of the present invention is to provide a semiconductor memory device to realize high speed cycles while improving the ease of use. The above-stated and other objects and novel features of the invention will become apparent from the description in this specification and the accompanying drawings.
What follows is a brief summary of a typical aspect of the present invention disclosed in this application. Thus, memory cells periodically needing a refresh operation to hold stored information are provided with a time-multiplexing mode of performing, when a first memory operation on a memory cell to read or write stored information or information to be stored and performing a second memory operation, having a different address designation from the first memory operation, or a refresh operation compete for the same time segment, the second memory operation or the refresh operation before or after the first memory operation, wherein the minimum access time needed for the first memory operation and the second memory operation or the refresh operation performed before or after the first memory operation is set shorter than the sum of the length of time required for the first memory operation and that required for the second memory operation or the refresh operation on condition that sets of information stored in the memory cells be not mutually affected in the first memory operation and the second memory operation or the refresh operation.
According to another typical aspect of the invention disclosed in this application, there are provided a memory array comprising a plurality of memory cells disposed to match a plurality of bit lines and a plurality of word lines and periodically needing a refresh operation to hold stored information; a precharging circuit for precharging the bit lines; an address selecting circuit for selecting a specific word line out of the plurality of word lines and a specific bit line out of the plurality of bit lines in accordance with an address signal; and a time-multiplexing control circuit for allocating a time segment, when a first memory operation on the memory cell to read or write stored information or information to be stored is instructed, for performing a second memory operation or the refresh operation, having a different address designation from the first memory operation, after the first memory operation, wherein the time-multiplexing control circuit allocates time segments for a first operation to release the bit lines from the precharge in accordance with the instruction of the first memory operation and to read information in the memory cells or write external information into the memory cell by performing operations to select a word line and a bit line in accordance with the address signal in the first memory operation, a first precharge operation to precharge the bit lines again, and for the second memory operation or the refresh operation by releasing the bit lines from the precharge and select a word line matching the second memory operation or the refresh operation.